Linearizing Voltage Control of MVDC Power Systems feeding Constant Power Loads: Stability Analysis under Saturation

Voltage stability in Medium Voltage DC (MVDC) power systems can be impaired due to the presence of tightly regulated power converters in the points of load. Such converters behave as instantaneous Constant Power Loads (CPLs) and can induce negative incremental resistance instabilities. Linearization via State Feedback (LSF) is a control technique which has proven to be effective to prevent CPL instability in MVDC systems. Theoretically, LSF can compensate any amount of CPL, but in practice it works until the interface converter output voltage is saturated. In this work, a controlled converter is employed to interface a generator to an MVDC bus feeding a CPL. A voltage stability study is presented, which applies in case of interface converter saturation. The study is suitable to assess voltage stability of the MVDC system, and to represent it graphically using state plane trajectories.