In this paper, we present a novel sorting algorithm which works trough a cascade of pipelined sorting units. The sorting device has been simulated in VHDL both at a behaviour level and at a gate level. The results of the simulation are shown.
VHDL design and simulation of a pipelined scalable architecture for high speed sorting
MUMOLO, ENZO
1996-01-01
Abstract
In this paper, we present a novel sorting algorithm which works trough a cascade of pipelined sorting units. The sorting device has been simulated in VHDL both at a behaviour level and at a gate level. The results of the simulation are shown.File in questo prodotto:
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