In this paper, we present a novel sorting algorithm which works trough a cascade of pipelined sorting units. The sorting device has been simulated in VHDL both at a behaviour level and at a gate level. The results of the simulation are shown.

VHDL design and simulation of a pipelined scalable architecture for high speed sorting

MUMOLO, ENZO
1996

Abstract

In this paper, we present a novel sorting algorithm which works trough a cascade of pipelined sorting units. The sorting device has been simulated in VHDL both at a behaviour level and at a gate level. The results of the simulation are shown.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11368/2789131
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