Digital processing systems have been proven to often outperform ana- log elaboration. Indeed, thanks to high-density DSPs and FPGAs, op- erations in digital domain give results that are impossible to achieve in other ways. On the other side, dealing with this great performance and fl exibility is not always straightforward: the processing chain needs to be accurately planned to reach the desired goals, avoiding erratic be- haviours in the digital domain. In this paper, we focus on the design and implementation of an FPGA-based digital processor that will be used in the electron beam position monitors of Elettra 2.0. After digi- tizing the 500 MHz beam signals from the pickups, the system executes a digital down conversion, followed by several fi ltering and demodulat- ing stages, in order to have a selectable data rate that is suitable for both diagnostics and feedback. The position calculation is also performed in FPGA as well, with the well-known difference-over-sum algorithm. Ac- cording to results provided by a fi xed-point simulation, the overall sys- tem has been implemented in an Intel Arria 10 FPGA, demonstrating the correct design functionality that meets the specifi ed requirements.
DESIGN AND IMPLEMENTATION OF AN FPGA-BASED DIGITAL PROCESSOR FOR BPM APPLICATIONS
Colja M.;Carrato S.;Brajnik G.;
2022-01-01
Abstract
Digital processing systems have been proven to often outperform ana- log elaboration. Indeed, thanks to high-density DSPs and FPGAs, op- erations in digital domain give results that are impossible to achieve in other ways. On the other side, dealing with this great performance and fl exibility is not always straightforward: the processing chain needs to be accurately planned to reach the desired goals, avoiding erratic be- haviours in the digital domain. In this paper, we focus on the design and implementation of an FPGA-based digital processor that will be used in the electron beam position monitors of Elettra 2.0. After digi- tizing the 500 MHz beam signals from the pickups, the system executes a digital down conversion, followed by several fi ltering and demodulat- ing stages, in order to have a selectable data rate that is suitable for both diagnostics and feedback. The position calculation is also performed in FPGA as well, with the well-known difference-over-sum algorithm. Ac- cording to results provided by a fi xed-point simulation, the overall sys- tem has been implemented in an Intel Arria 10 FPGA, demonstrating the correct design functionality that meets the specifi ed requirements.Pubblicazioni consigliate
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