The insertable B-Layer upgrade of the ATLAS pixel detector forsees the installation of a fourth pixel layer close to the beam pipe inside the current ATLAS pixel detector. A new readout chip (FE-I4) has been developed to match the increased requirements in terms of radiation hardness and hit occupancy. A new USE-based test system for ATLAS hybrid pixel detectors (USBpix) will serve as test bench for this new readout chip generation. The performance of USBpix is compared to the performance of the TPLL/TPCC system, used for testing the ATLAS pixel detector readout chips FE-I3 and modules. The main differences between the FE-I3 and the FE-I4 are summarized from the point of view of the test systems and the implementation of the main blocks for chip configuration, data storage and histogramming in the USBpix FPGA firmware for both chip generations is discussed. Results of the first measurements which were done using the FE-I4 emulator developed for debugging purposes are discussed. (C) 2010 Elsevier B.V. All rights reserved.
Development of a versatile and modular test system for ATLAS hybrid pixel detectors / Backhaus, M; Barbero, M; Gonella, L; Grosse-Knetter, J; Hugging, F; Kruger, H; Weingarten, J; Wermes, N. - In: NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH. SECTION A, ACCELERATORS, SPECTROMETERS, DETECTORS AND ASSOCIATED EQUIPMENT. - ISSN 0168-9002. - 650:1(2011), pp. 37-40. [10.1016/j.nima.2010.12.087]
Development of a versatile and modular test system for ATLAS hybrid pixel detectors
Gonella L;
2011-01-01
Abstract
The insertable B-Layer upgrade of the ATLAS pixel detector forsees the installation of a fourth pixel layer close to the beam pipe inside the current ATLAS pixel detector. A new readout chip (FE-I4) has been developed to match the increased requirements in terms of radiation hardness and hit occupancy. A new USE-based test system for ATLAS hybrid pixel detectors (USBpix) will serve as test bench for this new readout chip generation. The performance of USBpix is compared to the performance of the TPLL/TPCC system, used for testing the ATLAS pixel detector readout chips FE-I3 and modules. The main differences between the FE-I3 and the FE-I4 are summarized from the point of view of the test systems and the implementation of the main blocks for chip configuration, data storage and histogramming in the USBpix FPGA firmware for both chip generations is discussed. Results of the first measurements which were done using the FE-I4 emulator developed for debugging purposes are discussed. (C) 2010 Elsevier B.V. All rights reserved.Pubblicazioni consigliate
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